SIPO module sipomod(clk,clear, si, po); input clk, si,clear; output [3:0] po; reg [3:0] tmp; reg [3:0] po; always @(posedge clk) begin if (clear) tmp.

> for 6 to 16 bit programmable parallel to serial converter. Verilog/vhdl code for programmable parallel to serial converter. Author: anjali k.